The invention relates to an integrated electrical filter comprising at least one capacitor, at least one resistor, and a trimming circuit for adjusting the value of the product of the resistance of the resistor and the capacitance of the capacitor.
Both active and passive filters may be constructed using one or more capacitors and resistors. The filters may have high pass, low pass, band pass, band stop, and all pass characteristics. Low pass filters may be used as input filters for switched capacitor filters which, because they are sampled data filters, require the input signal to be band limited to prevent aliasing. Switched capacitor filters are being increasingly used due to their relative ease of integration. Similarly low pass filters are required as input filters for any signal processing circuits using sampled data techniques, e.g. other switched capacitor circuits and CCD circuits.
However, resistors and capacitors in integrated form have only a limited accuracy which prevents continuous time RC filters from having a closely defined, repeatable characteristic. Consequently it has been the general practice to use a discrete component filter in front of an integrated switched capacitor circuit or to use a much higher clock frequency which tends to increase the power dissipation. This, however, increases the cost of a system and consequently it is desirable to find a method of satisfactorily integrating a continuous time filter.
An integrated continuous time filter in which a more accurate RC time constant may be achieved is described in a paper entitled "Switched Resistor Filters. A Continuous Time Approach to Monolithic MOS Filter Design" by R. L. Geiger, P. E. Allen, and D. T. Ngo published in IEEE Transactions on Circuits and Systems, Vol. Cas-29, No. 5, May 1982, pages 306-315. This paper describes a filter in which each resistor is formed by field effect transistors (FETs) whose resistance is determined by the charge stored in, and hence the voltage across, a capacitor connected between their gate and source electrodes. Each resistor is formed by two FET's, only one being switched into the filter at a time, the other being connected in a trimming circuit which adjusts the voltage across the capacitor so that the resistance of the FET is made equal to the equivalent resistance of a switched capacitor. Thus when the FET is switched into the filter circuit the time constant of the filter capacitor and resistor depends only on the ratio between the switched capacitor and the filter capacitor and the clock frequency at which the switched capacitor is switched. When two or more capacitors are formed in a single integrated circuit it is comparatively straightforward to obtain an accurate ratio between the capacitance values. The clock frequency can also be defined accurately as it will normally be generated by an external circuit.
However, this known filter has the disadvantage that the resistance of the FETs have a non-linear relationship to the control voltage and this gives rise to inaccuracies in the resistance values. Also the resistance of different FETs for equal gate-source voltages are found to vary significantly due to differences in the voltages on the drain electrodes and on the back gates. Since the resistance of the FET is influenced by the source drain voltage the input signal will case modulation of the FET resistance, thus varying the filter characteristics with input signal amplitude. Further the use of two FETs for each resistor, only one of which is used at any instant, may give rise to crosstalk between the clock signals used for switching.
U.S. patent application Ser. No. 828,004 discloses an integrated electrical filter in which the trimming circuit comprises means for charging a further capacitor from a reference voltage source through a further resistor for a first period, means for removing the charge from the further capacitor in discrete increments during a second period, means for counting the number of increments required to remove the charge accumulated on the further capacitor during the first period, and means for adjusting the value of said at least one capacitor or said at least one resistor in dependence on the number of increments counted.
This filter has the advantage that the value of real resistors or capacitors is adjusted, thus avoiding the problems associated with the non-linear response of the FETs.
However, this filter does not take into account parasitic capacitances between the resistors and capacitors and the substrate.